Peggy Aycinena EDA Weekly Blood Sport – Securities & Security In an act of astonishing cunning - or astonishing vengeance - yesterday Cadence announced at 12:39 PM ET that they're withdrawing …

Mark Gilbert Careers Corner Here is the simple truth about your resume…

Dr. Russ Henke & Dr. Jack Horgan EDA & IP Commentary Commentary: Electronics IP Industry - An August 2008 Update

Verification IP Technologist for Mentor Graphics Corporation at San Jose, CA

Senior PLACE AND ROUTE ENGINEER R&D for EDA Careers at San Jose, CA

Field Applications Engineer - North East for Altium at Carslbad, CA

Major Accounts Manager for Intermap Technologies, Inc. at Englewood, CO

Snr Field Applications Engineer for Pulsic at Santa Clara, CA

Field Applications Engineer for ARITHMATICA at San Jose, CA

Hardware Verification With SystemVerilog: An Object-oriented Framework, by Mike Mintz, Robert Ekendahl.

Solutions Manual for Verilog Dhl, by Joseph Cavanagh.

High-Speed PCB Design Solutions - EMA Sponsored Seminar at 8:00 AM to 5:00 PM Seattle WA - Aug 26, 2008

High-Speed PCB Design Solutions - EMA Sponsored Seminar at 8:00 AM to 5:00 PM Vancouver BC Canada - Aug 28, 2008

Magnetics (Part 3) – The Core Model, Part 1 and Part 2 described the perfect and ideal transformer models, and how to add lossy elements to transformer models created with ideal …

Digital Design with Mentor EDA Tutorial, The purpose of this tutorial is to familiarize you with the basic set of Mentor Graphic EDA tools including Design Architect (or just plain da). DA …

Automated video algorithm implementation, This article presents an overview of a C-based design flow that enables designers to generate high-quality hardware for video algorithms. Algorithmic C synthesis is used to generate …